1. Field of the Invention
This invention relates generally to the field of semiconductor device timing synchronization and, more particularly, to a measure-controlled delay circuit with reduced playback error.
2. Description of the Related Art
Many high speed electronic systems possess critical timing requirements that dictate a need to generate a periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of computing integrated circuits and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew in time between significant edges of the internally generated clocks of all the components should be minimized, it is not enough to feed the external clock of the system to all the components. This is because different chips may have different manufacturing parameters, which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using a timing circuit, such as a digital delay locked loop (DDLL) circuit, to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. DDLL circuits typically require a relatively large number of clock cycles to synchronize. As a result of this significant lock period, DDLL circuits are not typically disabled after a lock is achieved to conserve power. DDLL circuits are also not well suited to handle large temperature or voltage shifts due to their slow response time. Instead of a DLL circuit, an open-loop topology may be used, such as a measure-controlled delay (MCD) circuit, where a timing measurement directly controls a variable delay. MCD circuits exhibit a fast lock capability (e.g., within 1–4 clock cycles after initialization). However, one drawback of such circuits is noise sensitivity, which may result in considerable jitter due to process, voltage, and temperature (PVT) variations.
One inherent problem associated with current MCD implementations is playback error. FIG. 1 illustrates a conventional MCD circuit 100. The MCD circuit 100 includes a measure delay array 110, a measure circuit 120, and a forward delay array 130. An external clock signal is provided to a buffer circuit 140, which is coupled to a delay monitor 150. The buffer circuit 140 represents the input circuitry of the device. It may include one or more buffers and/or other logic circuitry. The delay monitor 150 models the delay introduced into the external clock signal by the buffer circuit 140 and the delay introduced by the output circuitry. The clock signal exiting the delay monitor 150 thus approximates the actual output clock of the digital device if no clock synchronization circuitry were present. The external clock signal is also provided to the measure circuit 120 and the forward delay array 130.
The delay monitor 150 is coupled to a pulse generator 160. The pulse generator 160 is coupled to the measure delay array 110. Each rising edge of the clock signal entering the pulse generator 160 (e.g., simulated output clock signal) is converted to a narrow pulse (e.g., ˜800 ps wide) for propagation through the measure delay array 110. The pulse propagates through the measure delay array 110 until the measure circuit 120 is triggered. The measure circuit 120 includes a series of latches (not shown) that are triggered by the external clock signal. The particular latches triggered are those that correspond to the position of the pulse in the measure delay array 110 (i.e., as represented by “1”). As currently implemented, the entry point to the forward delay array 130 is the leftmost latch in the measure circuit 120 that was triggered. The number of triggered latches is determined by the unit propagation delay in the measure delay array 110 and the width of the pulse generated by the pulse generator 160.
Hence, there is an offset between the rising edge of the pulse that corresponds to the rising edge of the simulated output clock signal and the position that is locked into the forward delay array 130 (i.e., corresponding to the falling edge of the pulse). This misregistration is referred to as playback error. The playback error roughly corresponds to the width of the pulse that was propagated through the measure delay array 110.
Typical techniques for reducing playback error involve tuning out the playback error with static delay elements. The use of static delay elements assumes that the playback error will be constant across all PVT variations. This assumption becomes important as the sensitivity of the device to playback error increases. Certain MCD implementations require complete correspondence between the measurement and playback timing. In such cases, the use of static delay elements to tune out the playback error introduces instability into the system.
One such sensitive MCD implementation involves using a DDLL and an MCD circuit in combination. The MCD generates an initial measurement, and the DDLL takes over to maintain the lock and track variations over time. The dynamic range of the delay line (e.g., eight stages) used in the DDLL circuit is reduced, i.e., as compared to a stand-alone DDLL circuit. If the playback error is large compared to the width of the shortened delay line used in the DDLL, the circuit may fail to initialize and function.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.